ASIC для машинного навчання має проектуватися автоматично

Навряд чи хтось буде сперечатися з тим, що проектування ВІС (ASIC) ― це далеко не простий і не швидкий процес. Адже хочеться й треба, щоб було швидше: сьогодні видав алгоритм, а за тиждень забрав готовий цифровий проект. Адже справа в тому, що надспеціалізовані БІС ― це чи не штучний продукт. Такі рідко потрібні мільйонними партіями, на розробку яких можна витратити скільки завгодно грошей та людських ресурсів, якщо це треба зробити у найкоротший термін. Спеціалізовані, а від цього найефективніші для вирішення своїх завдань ASIC повинні обходитися у розробці дешевше, що стає мегаактуальним на сучасному етапі становлення машинного навчання. На цьому фронті вже не обійтися багажем, накопиченим комп’ютерним ринком і особливо проривами GPU на напрямі машинного навчання (ML).

Для прискорення проектування ASIC для завдань ML агентство DARPA започатковує нову програму ― Real Time Machine Learning (RTML). Програма з машинного навчання в реальному часі передбачає розробку компілятора або програмної платформи, які могли б автоматично проектувати архітектуру чіпа для конкретного ML-фрейморка. Платформа повинна автоматично аналізувати запропонований алгоритм для машинного навчання та набір даних для навчання цьому алгоритму, після чого на мові Verilog вона має видати код для створення спеціалізованої ASIC. Фахівці з розробки алгоритмів ML не мають знання проектувальників чіпів, а проектувальники рідко знайомі з принципами машинного навчання. Програма RTML повинна сприяти, щоб переваги тих і інших були об’єднані в автоматизованій платформі розробки ASIC для машинного навчання.

Протягом життєвого циклу роботи програми RTML знайдені рішення повинні будуть перевірятись у двох головних сферах застосування: робота в мережах 5G та обробка зображень. Також програма RTML та створені програмні платформи для автоматичного проектування прискорювачів ML будуть використовуватись для розробки та випробування нових алгоритмів ML та наборів даних. Тим самим, ще до проектування «кремнію» можна буде оцінити перспективи нових фреймворків. Партнером DARPA за програмою RTML виступить Національний науковий фонд (NSF), який також займається проблемами машинного навчання та розробкою алгоритмів ML. Розроблений компілятор буде переданий до NSF, а назад DARPA розраховує отримати компілятор та платформу з проектування алгоритмів ML. Надалі апаратне проектування та створення алгоритмів будуть йти комплексним рішенням, що призведе до появи самонавчання в реальному часі машинних систем.

What is an ASIC?

In June 2021, Google replaced millions of Intel’s CPU with home grown chips. This article provides and overview of the new ASIC developed by team Google to help optimizing the performance of YouTube servers. A custom-made ASIC (chip) rather than a general purpose ASIC (CPU), is design specifically by Google to perform a number specific tasks faster. In this article we will explore the world of ASICs and learn about their types and benefits.

What is an ASIC?

Figure 1 – An example of an ASIC An application-specific integrated circuit, or ASIC for short, is a chip created for a particular use or application, rather than for general-purpose use. They are usually made using silicon technology. Because of their uniqueness, they come in a many flavors and types. ASIC can be manufactured in multiple ways. They can be created from scratch to fit a very specific need or application, by creating a single IC with all the components needed (the resulting IC is called an SoC or System-on-Chip). ASIC are typically coded using a hardware description language like Verilog or VHDL. Before we can dive deeper into ASIC technology and find out the benefits and possible drawbacks, we have to look at the history and understand where it all started from.

The History of ASICs

In the early days, ASICs started as circuits using the gate array technology, with the introduction in 1967 of bipolar DTL (Diode-Transistor Logic) and TTL (Transistor-Transistor Logic) gate arrays through the Micromatrix family from the Fairchild Semiconductor company. After CMOS (Complementary Metal Oxide Semiconductor) technology hit the market, ASICs began to grow in size, with the first CMOS gate arrays being developed in 1974 by Robert Lipp for International Microcircuits Inc. MOS technology also got standardized by Fairchild and Motorola in the 1970s, when the Micromosaic and Polycell standard cells were created. This technology was successfully commercialized only later by VLSI Technology starting from 1979 and by LSI Logic from 1981. A successful commercially viable application for mass-market users was introduced in 1981 through the ZX81 8-bit chip and in 1982 through the ZX Spectrum personal computers. In this period, gate arrays consisted of a few thousand gates, which is now referred to as mid-scale integration. The customization was done by varying a metal and/or polysilicon interconnect mask(s).

ASIC Variants

1. Requirements engineering, which is the logical continuation of requirements analysis and it is done by a team of engineers who condense the required functions needed.
2. RTL (Register Transfer Level) design. During this stage a team of designers write the HDL code needed for the logic of the ASIC.
3. Functional verification. Using a suite of testing methods, the logic is verified before being written to the ASIC, as the resulting IC is no longer programmable. Logic errors are very costly and are to be avoided, so a full test coverage is definitely recommended.
4. Logic synthesis. During this step the RTL design is brought to life, being printed into the standard cells and the connections between them, all of which forms a gate-level netlist.
5. Placement. The standard cells are placed on their corresponding spot on the IC such as the placement is optimally done. The optimality is ensured by using a few specific constraints.
6. Routing. An electronic routing tool is used to tur
   n the netlist into a sufficiently optimal network of electrical connections, which connect all the standard cells as specified. The result is usually a file which can be printed out as a photomask and then used to etch the actual physical IC at fabs or foundries.
7. Sign-off. After the final layout is done, a series of calculations are done to determine the parasitic resistances and capacitances and to determine the delay information (using static timing analysis). When all the computations are done and are verified to be valid, the sign-off is given and the photomask can be sent to fabs for production.

These steps form what is called ASIC design flow and by sticking to this, the final device will always be correctly implemented, unless flaws are introduced at the manufacturing foundry or in shipping.

As for gate-arrays and semi-custom design, it has certain benefits beyond the standard cells, but it comes at the cost of longer design and development cycles. The semi-custom approach is a compromise between quick design times and performance.

Today, gate-array ASICs are usually present in the form of structured ASICs that consist of a large CPU, digital signal processors, peripherals, standard interfaces, static RAM and a block of reconfigurable/programmable uncommitted logic.

Full-custom design is usually the most cost intensive ASIC development process, as the design must start from the semiconductor level and use HDLs to describe every layer of the ASIC. This approach is used by processor designers, like Intel, AMD and Nvidia, to create further optimized ASICs.

How are ASICs better?

Figure 4 – ASIC advantages and disadvantages

Advantages that ASICs have over standard ICs are the reduced size, the better performance at lower power requirements, IP protection and lower manufacturing costs at large scales. But there are also the disadvantages, like the increased up-front cost of developing an ASIC and the increased difficulty in designing and testing, but these can be mitigated well by doing proper market analysis for the product that you have in mind before committing a large sum of funding to it.

Standard-cell ASICs are the cheapest of the three main types of ASICs and are usually an intermediary between semi-custom design ICs and fully-custom ICs. They have quick turnaround times, but lack the detail and precision of full-custom designed chips.

Semi-custom ASICs are a bit more expensive, but can have larger numbers of logic gates. Difficulties arise when it comes to routing, as some interconnects might require migration, which would increase the array needed, further driving up the cost. Also, these ICs can never use 100% of the available silicon wafer.

Full-custom ASICs are the most well-known and have big advantages and drawbacks. They can use less area (and therefore components cost less), offer higher performance and integrate other previously tested components, like microprocessor cores, forming a SoC. The disadvantages associated with this method of designing ASICs are the increased manufacturing and design times, increased engineering costs, added complexity on the CAD (Computer-Assisted Design) and EDA (Electronic Design Automation) systems, requiring a more qualified and experienced team of designers and engineers.

When and how to use ASICs?

Seeing as there is a lot of variety in how you can make an ASIC, you need to be able to choose the best technology to power your project or product.

For a low-volume production series or prototypes, ASICs are not economically viable, as the engineering costs are extremely high. Therefore, ASICs are recommended for high-volume production series, where the costs can be dampened across many devices.

Another application that is well-suited for ASICs is making an existing device smaller and/or more energy efficient and/or more performant. This is the reason why devices are constantly getting smaller, as ASICs penetrate the market further and further and drive the miniaturization of all devices, from the chips that provide the functionality of your car and phone, to the chips that power your fridge or automated coffee maker.

If you are worried about some other company or individual stealing your design, ASICs are a great way to ensure your design stays secret forever, as the actual design of ASICs prevents the theft of IP. It is very difficult to reverse engineer an Intel processor, for example. Thus, despite being on the market for over 50 years, no one has managed to figure out how to create an exact copy of their design.

Introduction to ASIC Technology | Different Types, Design Flow, Applications

In this tutorial, we will see a basic introduction to ASIC, what are the different types of ASIC design techniques, the ASIC design flow, applications and many more.

Introduction

In a broad sense, an Application Specific Integrated Circuit or simply an ASIC can be defined as an integrated circuit customized for a particular application or end-use rather than using it for general purpose. Some basic examples of ASICs are the IC in a DVD Player to decode the information on an optical disc or an IC designed as a Charge Controller for Lithium Ion batteries.

ASICs are quite different from other standard ICs like Microprocessors or Memories as these are designed to be used in a wide range of applications. In contrast, an ASIC can only be used in the application it was specifically designed to run.

Due to the application specific custom nature of the ASICs, they often pack more functionality at the same time being small in size, consuming less power and dissipating less heat when compared to a standard IC solution. The other main difference between standard ICs like Memories, for example and ASICs is that the designer of the ASIC can directly be the customer, who might have a clearer idea of the application.

Since the early 1980s, the world of integrated circuits has been highly influenced by ASICs. They are responsible for the expansion of the semiconductor industry, change in the business model of the integrated circuits and significant increase in IC designs and design engineers.

ASICs also influenced the whole ecosystem of the semiconductor design and manufacturing like system design, fabrication and manufacturing process, testing and packaging and the CAD tools.

A Brief History of ASICs

The origin of ASICs can be traced back to at least 20 tears before the development of Masked ROM (Read-only Memory). In the early 1970s, the concept of Gate Arrays and Standard Cells have been introduced but during the 1980s, the ASIC technology took a prominent place in the IC market throughout the World.

It is during this period that several semiconductor manufacturers and vendors, particularly from Japan, dominated the ASIC market and are regarded as ASIC Specialists.

What are the Different Types of ASIC?

The history of ASIC designs and technology can be characterized by the continuous growth and evolution of various design styles of ASIC. Statistically speaking, the CMOS based gate array style ASICs are the dominant type but there are several other types of ASIC designs.

Basically, all ASICs can be categorized into three types. They are:

The semi-custom ASICs are again divided into Gate Array based designs and Cell based designs. Gate Arrays are further divided into Channelled and Channel-less Arrays while Cell based designs are further divided into Standard Cell and Macrocell.

Coming to Programmable ICs, all the Programmable Logic Devices like PAL, PLA, EPROM based PLD (EPLD), EEPROM based PLD (EEPLD), and field programmable devices like FPGA come under this category.

The following image shows the different types of ASIC and also the sub-categories in each type.

Let us now briefly see some of the important types of ASICs.

Full-Custom ASIC

In Full-Custom ASIC, all the logic cells, circuits and layouts are
designed specifically for that particular ASIC from the ground up. The designer may choose a full-custom ASIC design only if he thinks that either the existing libraries are not fast enough or the logic cells are not small or the power consumption is high.

The main advantages of full-custom ASICs over other IC designs are it delivers the highest possible performance at the smallest possible die size. But this high performance and small size comes at a price of increased design time, complex design and overall cost of the IC itself.

Some of most common full-custom ASISs are Microprocessors, Memories, Analog Processors, Analog / Digital Communication devices, Sensors, Transducers, high-voltage ICs for Automobiles, etc.

The following is a sample design of a CMOS based 2-input NAND gate, where every layer is defined.

Semi-Custom ASIC

To shorten the design time and cut down the cost of full-custom ASICs, numerous other design approaches have been developed and these are called as Semi-Custom ASIC Designs. Usually, the lowest level of hierarchy involved in semi-custom design is the logic level or gate level. This is in contrast to full-custom job, where the design and layout individual transistor might be involved.

As mentioned earlier, the semi-custom ASIS design can be further divided into Gate Arrays and Standard Cells. Let us see a little bit about these types.

Gate Array ASIC

In Gate Array based ASICs, p and n types transistors are predefined on a silicon wafer as arrays. Based on the design from the customer and the interconnections obtained from the design, the silicon vendor provides these base wafers. Therefore, the base wafer is specific to the customer as it is designed based on the customer provided connections between the transistors of the gate array.

The gate arrays are again divided into two types called the Channelled Gate Array and the Channel-less Gate Array. In channelled gate arrays, the interconnections between the logic cells are performed within the predefined channels between the rows of the logic cells. In case of channel-less gate arrays, the connections are made on an upper metal layer on top of the logic cells.

Standard Cell based ASIC

A Standard Cell based ASIC uses predesigned logic cells like Gates, Multiplexers, Flip-flops, Adders etc. These logic cells are known as Standard Cells that are already designed and stored in a library. This library is imported into the CAD tool and the design can performed using the components of the library as inputs.

Typically, Standard Cell based designs are organized as rows of constant height cells on the chip, just like a row of bricks. When combined with logic-level components, standard cell-based designs can be used to implement complex functions like Multipliers and Memory Arrays.

The standard cell design may also contain a larger and more complex predesigned cells like Microcontrollers or Microprocessors. These larger cells are called as Megacells.

Design Flow

Until now, you have seen a brief introduction to ASIC and also few important types of ASICs. In this section let us try to briefly understand the specific process flow and procedures involved in designing and developing an ASIC.

The following image shows a typical design flow involved in designing a semicustom ASIC. It can be basically divided into 10 steps.

• Design Entry: In the step, the logic design is created using a Hardware Description Language (HDL) like VHDL or Verilog or with the help of Schematic entry.
• Logic Synthesis: Once the logic is designed using HDL or Schematic entry, the next step is to extract the description of the logic cells and their interconnections. This information is also called as Netlist.
• System Partitioning: The next step is to logically divide the entire system into small ASIC sized blocks.
• Pre-layout Simulation: Before going into the actual physical layout of the design, a simulation tool checks the circuit for proper working. In fact, this process is performed at every step so that if any errors are found, then it would be easy to correct them at this stage itself. The process until this step is usually regarded as Logical Design. The steps after this are related to the actual physical layout of the design.
• Floorplanning: The first step in the physical design is arrange all the blocks of the circuit on the chip.
• Placement: In this step, the location of the logic cells in a block are set.
• Routing: Once the placement of the blocks and cells is completed, then it is time to create the connections between the cells and the blocks.
• Extraction: The next step is to determine the resistance and capacitance of the interconnections previously made, since they decide the delay of the signal. Also, the delays are calculated at this stage.
• Post-layout Simulation: Once the physical design is complete, the circuit is again tested for working. The delays previously calculated are also taken into consideration for the simulation process.
• Design Rule Check (DRC): Final step is to verify the layout of the entire circuit and check whether it complies with the design rule specifications.

Applications

The area of applications of ASICs is very wide as they are basically used everywhere where there is a need for performance, customization and size. Some of the common categories of application are mentioned below.

• Sensors and Transducers
• Automotive and Avionic Components
• Satellite, Radar and related Communication processors
• Microprocessors, Memories, Microcontrollers

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